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general description the max1185 is a +3v, dual 10-bit analog-to-digital converter (adc) featuring fully-differential wideband track-and-hold (t/h) inputs, driving two pipelined, nine-stage adcs. the max1185 is optimized for low- power, high dynamic performance applications in imaging, instrumentation, and digital communication applications. this adc operates from a single +2.7v to +3.6v supply, consuming only 105mw while delivering a typical signal-to-noise ratio (snr) of 59.5db at an input frequency of 7.5mhz and a sampling rate of 20msps. digital outputs a and b are updated alternat- ing on the rising (cha) and falling (chb) edge of the clock. the t/h driven input stages incorporate 400mhz (-3db) input amplifiers. the converters may also be operated with single-ended inputs. in addition to low operating power, the max1185 features a 2.8ma sleep mode as well as a 1? power-down mode to conserve power during idle periods. an internal +2.048v precision bandgap reference sets the full-scale range of the adc. a flexible reference structure allows the use of this internal or an externally derived reference, if desired for applications requiring increased accuracy or a different input voltage range. the max1185 features parallel, multiplexed, cmos- compatible three-state outputs. the digital output for- mat can be set to two? complement or straight offset binary through a single control pin. the device provides for a separate output power supply of +1.7v to +3.6v for flexible interfacing. the max1185 is available in a 7mm x 7mm, 48-pin tqfp package, and is specified for the extended industrial (-40? to +85?) tempera- ture range. pin-compatible, nonmultiplexed. high-speed versions of the max1185 are also available. please refer to the max1180 data sheet for 105msps, the max1181 data sheet for 80msps, the max1182 data sheet for 65msps, the max1183 data sheet for 40msps, and the max1184 data sheet for 20msps. applications high resolution imaging i/q channel digitization multichannel if sampling instrumentation video application ultrasound features single +3v operation excellent dynamic performance: 59.5db snr at f in = 7.5mhz 74db sfdr at f in = 7.5mhz low power: 35ma (normal operation) 2.8ma (sleep mode) 1? (shutdown mode) 0.02db gain and 0.25 phase matching wide ?vp-p differential analog input voltage range 400mhz, -3db input bandwidth on-chip +2.048v precision bandgap reference single 10-bit bus for multiplexed, digital outputs user-selectable output format ?two? complement or offset binary 48-pin tqfp package with exposed paddle for improved thermal dissipation max1185 dual 10-bit, 20msps, +3v, low-power adc with internal reference and multiplexed parallel outputs ________________________________________________________________ maxim integrated products 1 d1a/b d0a/b ognd ov dd ov dd ognd a/b n.c. n.c. n.c. n.c. n.c. com v dd gnd ina+ ina- v dd gnd inb- inb+ gnd v dd clk 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 48-tqfp-ep gnd v dd gnd v dd t/b sleep pd oe n.c. n.c. n.c. n.c. 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 refn refp refin refout d9a/b d8a/b d7a/b d6a/b d5a/b d4a/b d3a/b d2a/b max1185 pin configuration 19-2175; rev 0; 10/01 ordering information part temp. range pin-package MAX1185ECM -40 c to +85 c 48 tqfp-ep for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com.
max1185 dual 10-bit, 20msps, +3v, low-power adc with internal reference and multiplexed parallel outputs 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = +3v, ov dd = +2.5v, 0.1f and 1f capacitors from refp, refn, and com to gnd; refout connected to refin through a 10k ? resistor, v in = 2vp-p (differential w.r.t. com), c l = 10pf at digital outputs (note 5), f clk = 20mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd , ov dd to gnd ...............................................-0.3v to +3.6v ognd to gnd.......................................................-0.3v to +0.3v ina+, ina-, inb+, inb- to gnd ...............................-0.3v to v dd refin, refout, refp, refn, com, clk to gnd............................................-0.3v to (v dd + 0.3v) oe , pd, sleep, t/b, d9a/b d0a/b, a/b to ognd .......................................-0.3v to (ov dd + 0.3v) continuous power dissipation (t a = +70 c) 48-pin tqfp (derate 12.5mw/ c above +70 c).......1000mw operating temperature range ...........................-40 c to +85 c junction temperature ......................................................+150 c storage temperature range .............................-60 c to +150 c lead temperature (soldering, 10s) .................................+300 c parameter symbol conditions min typ max units dc accuracy resolution 10 bits integral nonlinearity inl f in = 7.5mhz 0.5 1.5 lsb differential nonlinearity dnl f in = 7.5mhz, no missing codes guaranteed 0.25 1.0 lsb offset error < 1 1.7 % fs gain error 0 2 % fs analog input differential input voltage range v diff differential or single-ended inputs 1.0 v common-mode input voltage range v cm v dd /2 0.5 v input resistance r in switched capacitor load 100 k ? input capacitance c in 5pf conversion rate maximum clock frequency f clk 20 mhz cha 5 data latency chb 5.5 clock cycles dynamic characteristics (f clk = 20mhz, 4096-point fft) f ina or b = 7.5mhz, t a = +25 c 57.3 59.5 signal-to-noise ratio snr f ina or b = 12mhz 59.4 db f ina or b = 7.5mhz, t a = +25 c 57 59.4 signal-to-noise and distortion sinad f ina or b = 12mhz 59.2 db f ina or b = 7.5mhz, t a = +25 c6474 spurious-free dynamic range sfdr f ina or b = 12mhz 72 dbc
max1185 dual 10-bit, 20msps, +3v, low-power adc with internal reference and multiplexed parallel outputs _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = +3v, ov dd = +2.5v, 0.1f and 1f capacitors from refp, refn, and com to gnd; refout connected to refin through a 10k ? resistor, v in = 2vp-p (differential w.r.t. com), c l = 10pf at digital outputs (note 5), f clk = 20mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units f ina or b = 7.5mhz -74 third-harmonic distortion hd3 f ina or b = 12mhz -72 dbc f ina or b = 11.9852mhz at -6.5db fs intermodulation distortion imd f i n a o r b = 12.8934m h z at - 6.5d b fs ( n ote 2) -76 dbc f ina or b = 7.5mhz, t a = +25 c -72 -64 total harmonic distortion (first 4 harmonics) thd f ina or b = 12mhz -71 dbc small-signal bandwidth input at -20db fs, differential inputs 500 mhz full-power bandwidth fpbw input at -0.5db fs, differential inputs 400 mhz aperture delay t ad 1ns aperture jitter t aj 2ps rms overdrive recovery time for 1.5 ? full-scale input 2 ns differential gain 1% differential phase 0.25 d egr ees output noise ina+ = ina- = inb+ = inb- = com 0.2 lsb rms internal reference reference output voltage refout 2.048 3% v reference temperature coefficient tc ref 60 ppm/ c load regulation 1.25 mv/ma buffered external reference (v refin = +2.048v) refin input voltage v refin 2.048 v positive reference output voltage v refp 2.012 v negative reference output voltage v refn 0.988 v differential reference output voltage range ? vref ? vref = vrefp - vrefn 0.98 1.024 1.07 v refin resistance r refin >50 m ?
max1185 dual 10-bit, 20msps, +3v, low-power adc with internal reference and multiplexed parallel outputs 4 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = +3v, ov dd = +2.5v, 0.1f and 1f capacitors from refp, refn, and com to gnd; refout connected to refin through a 10k ? resistor, v in = 2vp-p (differential w.r.t. com), c l = 10pf at digital outputs (note 5), f clk = 20mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units maximum refp, com source current i source 5ma maximum refp, com sink current i sink -250 a maximum refn source current i source 250 a maximum refn sink current i sink -5 ma unbuffered external reference (v refin = agnd, reference voltage applied to refp, refn, and com) refp, refn input resistance r refp , r refn measured between refp and com, and refn and com 4k ? differential reference input voltage ? v ref ? v ref = v refp - v refn 1.024 10% v com input voltage v com v dd /2 10% v refp input voltage v refp v com + ? v ref /2 v refn input voltage v refn v com - ? v ref /2 v digital inputs (clk, pd, oe , sleep, t/b) clk 0.8 ? v dd input high threshold v ih pd, oe , sleep, t/b 0.8 ? ov dd v clk 0.2 ? v dd input low threshold v il pd, oe , sleep, t/b 0.2 ? ov dd v input hysteresis v hyst 0.1 v i ih v ih = ov dd or v dd (clk) 5 input leakage i il v il = 0 5 a input capacitance c in 5pf digital outputs (d0a/b d9a/b, a/b) output voltage low v ol i sink = -200a 0.2 v output voltage high v oh i source = 200a ov dd - 0.2 v three-state leakage current i leak oe = ov dd 10 a three-state output capacitance c out oe = ov dd 5pf
max1185 dual 10-bit, 20msps, +3v, low-power adc with internal reference and multiplexed parallel outputs _______________________________________________________________________________________ 5 electrical characteristics (continued) (v dd = +3v, ov dd = +2.5v, 0.1f and 1.0f capacitors from refp, refn, and com to gnd; refout connected to refin through a 10k ? resistor, v in = 2vp-p (differential w.r.t. com), c l = 10pf at digital outputs (note 5), f clk = 20mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units power requirements analog supply voltage range v dd 2.7 3.0 3.6 v output supply voltage range ov dd 1.7 2.5 3.6 v operating, f ina or b = 7.5mhz at -0.5db fs 35 50 sleep mode 2.8 ma analog supply current i vdd shutdown, clock idle, pd = oe = ov dd 115a operating, c l = 15pf, f ina or b = 7.5mhz at -0.5db fs 4ma sleep mode 100 output supply current i ovdd shutdown, clock idle, pd = oe = ov dd 210 a operating, f ina or b = 7.5mhz at -0.5db fs 105 150 sleep mode 8.4 mw power dissipation pdiss shutdown, clock idle, pd = oe = ov dd 345w offset 0.2 mv/v power-supply rejection ratio psrr gain 0.1 %/v timing characteristics clk rise to cha output data valid t doa figure 3 (note 3) 5 8 ns clk fall to chb output data valid t dob figure 3 (note 3) 5 8 ns clock rise/fall to a/b rise/fall time t da/b 6ns output enable time t enable figure 4 10 ns output disable time t disable figure 4 1.5 ns clk pulse width high t ch figure 3, clock period: 50ns 25 7.5 ns clk pulse width low t cl figure 3, clock period: 50ns 25 7.5 ns wakeup from sleep mode (note 4) 0.51 wake-up time t wake wakeup from shutdown (note 4) 1.5 s channel-to-channel matching crosstalk f ina or b = 7.5mhz at -0.5db fs -70 db gain matching f ina or b = 7.5mhz at -0.5db fs 0.02 0.2 db phase matching f ina or b = 7.5mhz at -0.5db fs 0.25 d eg r ees note 1: snr, sinad, thd, sfdr, and hd3 are based on an analog input voltage of -0.5db fs referenced to a +1.024v full-scale input voltage range. note 2: intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. this number i s 6db or better, if referenced to the two-tone envelope. note 3: digital outputs settle to v ih , v il . parameter guaranteed by design. note 4: with refin driven externally, refp, com, and refn are left floating while powered down. note 5: equivalent dynamic performance is obtainable over full ov dd range with reduced c l .
max1185 dual 10-bit, 20msps, +3v, low-power adc with internal reference and multiplexed parallel outputs 6 _______________________________________________________________________________________ typical operating characteristics (v dd = +3v, ov dd = +2.5v, v refin = +2.048v, differential input at -0.5db fs, f clk = 20.00057mhz, c l 10pf, t a = +25 c, unless otherwise noted.) -100 -80 -90 -60 -70 -40 -50 -30 -10 -20 0 0 234 1 567 9 810 fft plot cha (differential input, 8192-point data record) max1185 toc01 analog input frequency (mhz) amplitude (db) cha f clk = 20.0005678mhz f ina = 5.9742906mhz f inb = 7.5343935mhz aina = -0.525db fs hd3 hd2 -100 -80 -90 -60 -70 -40 -50 -30 -10 -20 0 0 234 1 567 9 810 fft plot chb (differential input, 8192-point data record) max1185 toc02 analog input frequency (mhz) amplitude (db) chb f clk = 20.0005678mhz f ina = 5.9742906mhz f inb = 7.5243935mhz aina = -0.462db fs hd3 hd2 -100 -80 -90 -60 -70 -40 -50 -30 -10 -20 0 0 234 1 567 9 810 fft plot cha (differential input, 8192-point data record) max1185 toc03 analog input frequency (mhz) amplitude (db) cha f clk = 20.0005678mhz f ina = 7.5343935mhz f inb = 11.9852035mhz aina = -0.489db fs hd3 hd2 -100 -80 -90 -60 -70 -40 -50 -30 -10 -20 0 0 234 1 567 9 810 fft plot chb (differential input, 8192-point data record) max1185 toc04 analog input frequency (mhz) amplitude (db) chb f clk = 20.0005678mhz f ina = 7.5343935mhz f inb = 11.9852035mhz aina = -0.471db fs hd3 hd2 -100 -80 -90 -60 -70 -40 -50 -30 -10 -20 0 0 234 1 567 9 810 two-tone imd plot (differential input, 8192-point data record) max1185 toc05 analog input frequency (mhz) amplitude (db) imd2 imd3 imd3 f clk = 20.0005678mhz f in1 = 11.9852035mhz f in2 = 12.8934324mhz ain = -6.5db fs two-tone envelope = -0.498db fs f in2 f in1 57 56 55 59 58 60 61 1 10 100 signal-to-noise ratio vs. analog input frequency max1185 toc06 analog input frequency (mhz) snr (db) chb cha 62 60 58 54 56 1 10 100 signal-to-noise plus distortion vs. analog input frequecny max1185 toc07 analog input frequency (mhz) sinad (db) chb cha -74 -77 -80 -71 -68 -65 total harmonic distortion vs. analog input frequency max1185 toc08 analog input frequency (mhz) thd (dbc) 1 10 100 cha chb 60 64 72 68 76 80 spurious-free dynamic range vs. analog input frequency max1185 toc09 analog input frequency (mhz) sfdr (dbc) 1 10 100 cha chb
max1185 dual 10-bit, 20msps, +3v, low-power adc with internal reference and multiplexed parallel outputs _______________________________________________________________________________________ 7 -8 -4 -6 0 -2 4 2 6 1 10 100 1000 full-power input bandwidth vs. analog input frequency, single-ended max1185 toc10 analog input frequency (mhz) gain (db) -8 -4 -6 0 -2 4 2 6 1 10 100 1000 small-signal input bandwidth vs. analog input frequency, single-ended max1185 toc11 analog input frequency (mhz) gain (db) v in = 100mv p-p 35 45 40 55 50 60 65 -20 0 signal-to-noise ratio vs. input power (f in = 7.5343935mhz) max1185 toc12 input power (db fs) snr (db) -12 -16 -8 -4 35 45 40 55 50 60 65 -20 0 signal-to-noise plus distortion vs. input power (f in = 7.5343935mhz) max1185 toc13 input power (db fs) sinad (db) -12 -16 -8 -4 -80 -76 -66 -72 -64 -60 -20 -12 -16 -8 -4 0 total harmonic distortion vs. input power (f in = 7.5343935mhz) max1185 toc14 input power (db fs) thd (dbc) 65 60 75 70 80 85 -20 -12 -16 -8 -4 0 spurious-free dynamic range vs. input power (f in = 7.5343935mhz) max1185 toc15 input power (db fs) sfdr (dbc) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0 256 128 384 512 640 768 896 1024 integral nonlinearity (best end-point fit) max1185 toc16 digital output code inl (lsb) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0 256 128 384 512 640 768 896 1024 differential nonlinearity max1185 toc17 digital output code dnl (lsb) -0.1 -0.2 0.1 0 0.3 0.2 0.4 -40 85 gain error vs. temperature max1185 toc18 temperature ( c) gain error (%fs) 10 -15 35 60 chb cha typical operating characteristics (continued) (v dd = +3v, ov dd = +2.5v, v refin = +2.048v, differential input at -0.5db fs, f clk = 20.00057mhz, c l 10pf, t a = +25 c, unless otherwise noted.)
max1185 dual 10-bit, 20msps, +3v, low-power adc with internal reference and multiplexed parallel outputs 8 _______________________________________________________________________________________ -0.4 -0.2 -0.3 0 -0.1 0.1 0.2 -40 85 offset error vs. temperature max1185 toc19 temperature ( c) offset error (%fs) 10 -15 35 60 chb cha 33 34 36 35 37 38 2.70 3.00 2.85 3.15 3.30 3.45 3.60 analog supply current vs. analog supply voltage max1185 toc20 v dd (v) i vdd (ma) 28 30 34 32 36 38 -40 10 -15 35 60 85 analog supply current vs. temperature max1185 toc21 temperature ( c) i vdd (ma) 0 0.05 0.15 0.10 0.20 0.25 2.70 3.00 2.85 3.15 3.30 3.45 3.60 analog power-down current vs. analog power supply max1185 toc22 v dd (v) i vdd ( a) oe = pd = ov dd 50 56 68 62 74 80 30 40 50 60 70 80 sfdr, snr, thd, sinad vs. clock duty ctcle max1185 toc23 clock duty cycle (%) sfdr, snr, thd, sinad (db) sfdr f in = 7.5343935mhz snr sinad thd 2.0000 2.0020 2.0060 2.0040 2.0080 2.0100 2.70 3.00 2.85 3.15 3.30 3.45 3.60 internal reference voltage vs. analog supply voltage max1185 toc24 v dd (v) v refout (v) 1.994 2.002 1.998 2.006 2.010 2.014 -40 85 internal reference voltage vs. temperature max1185 toc25 temperature ( c) v reout (v) 10 -15 35 60 0 21,000 14,000 7,000 28,000 35,000 42,000 49,000 56,000 63,000 70,000 output noise histogram (dc input) max1185 toc26 digital output code counts 64,515 n 869 n-1 152 n+1 0 n+2 0 n-2 typical operating characteristics (continued) (v dd = +3v, ov dd = +2.5v, v refin = +2.048v, differential input at -0.5db fs, f clk = 20.00057mhz, c l 10pf, t a = +25 c, unless otherwise noted.)
max1185 dual 10-bit, 20msps, +3v, low-power adc with internal reference and multiplexed parallel outputs _______________________________________________________________________________________ 9 pin description pin name function 1 com common-mode voltage input/output. bypass to gnd with a 0.1f capacitor. 2, 6, 11, 14, 15 v dd analog supply voltage. bypass to gnd with a capacitor combination of 2.2f in parallel with 0.1f. 3, 7, 10, 13, 16 gnd analog ground 4 ina+ channel a positive analog input. for single-ended operation, connect signal source to ina+. 5 ina- channel a negative analog input. for single-ended operation, connect ina- to com. 8 inb- channel b negative analog input. for single-ended operation, connect inb- to com. 9 inb+ channel b positive analog input. for single-ended operation, connect signal source to inb+. 12 clk converter clock input 17 t/b t/b selects the adc digital output format. high: two s complement. low: straight offset binary. 18 sleep sleep mode input. high: deactivates the two adcs, but leaves the reference bias circuit active. low: normal operation. 19 pd power-down input. high: power-down mode. low: normal operation. 20 oe output enable input. high: digital outputs disabled. low: digital outputs enabled. 21 29 n.c. do not connect. 30 a/b a/b data indicator. this digital output indicates cha data (a/b = 1) or chb data (a/b = 0) to be present on the output. a/b follows the external clock signal with typically 6ns delay. 31, 34 ognd output driver ground 32, 33 ov dd output driver supply voltage. bypass to ognd with a capacitor combination of 2.2f in parallel with 0.1f. 35 d0a/b three-state digital output, bit 0 (lsb). depending on status of a/b, output data reflects channel a or channel b data. 36 d1a/b three-state digital output, bit 1. depending on status of a/b, output data reflects channel a or channel b data. 37 d2a/b three-state digital output, bit 2. depending on status of a/b, output data reflects channel a or channel b data. 38 d3a/b three-state digital output, bit 3. depending on status of a/b, output data reflects channel a or channel b data. 39 d4a/b three-state digital output, bit 4. depending on status of a/b, output data reflects channel a or channel b data. 40 d5a/b three-state digital output, bit 5. depending on status of a/b, output data reflects channel a or channel b data.
detailed description the max1185 uses a nine-stage, fully-differential, pipelined architecture (figure 1) that allows for high- speed conversion while minimizing power consumption. samples taken at the inputs move progressively through the pipeline stages every half-clock cycle. including the delay through the output latch, the total clock-cycle latency is five clock cycles. 1.5-bit (2-comparator) flash adcs convert the held input voltages into a digital code. the digital-to-analog con- verters (dacs) convert the digitized results back into analog voltages, which are then subtracted from the original held input signals. the resulting error signals are then multiplied by two and the residues are passed along to the next pipeline stages, where the process is repeated until the signals have been processed by all nine stages. digital error correction compensates for adc comparator offsets in each of these pipeline stages and ensures no missing codes. both input channels are sampled on the rising edge of the clock and the resulting data is multiplexed at the output. cha data is updated on the rising edge (five clock cycles later) and chb data is updated on the falling edge (5.5 clock cycles later) of the clock signal. the a/b indicator follows the clock signal with a typical delay time of 6ns and remains high when cha data is updated and low when chb data is updated. input track-and-hold (t/h) circuits figure 2 displays a simplified functional diagram of the input track-and-hold (t/h) circuits in both track and hold mode. in track mode, switches s1, s2a, s2b, s4a, s4b, s5a, and s5b are closed. the fully differential circuits sample the input signals onto the two capacitors (c2a and c2b) through switches s4a and s4b. s2a and s2b set the common mode for the amplifier input, and open simultaneously with s1, sampling the input waveform. switches s4a and s4b are then opened before switches s3a and s3b connect capacitors c1a and c1b to the out- put of the amplifier and switch s4c is closed. the result- ing differential voltages are held on capacitors c2a and c2b. the amplifiers are used to charge capacitors c1a and c1b to the same values originally held on c2a and c2b. these values are then presented to the first stage quantizers and isolate the pipelines from the fast-chang- ing inputs. the wide input bandwidth t/h amplifiers allow the max1185 to track and sample/hold analog inputs of high frequencies (> nyquist). both adc inputs (ina+, inb+, ina-, and inb-) can be driven either differentially or single-ended. match the impedance of ina+ and ina- as well as inb+ and inb- and set the common-mode volt- age to midsupply (v dd /2) for optimum performance. max1185 dual 10-bit, 20msps, +3v, low-power adc with internal reference and multiplexed parallel outputs 10 ______________________________________________________________________________________ pin description (continued) pin name function 41 d6a/b three-state digital output, bit 6. depending on status of a/b, output data reflects channel a or channel b data. 42 d7a/b three-state digital output, bit 7. depending on status of a/b, output data reflects channel a or channel b data. 43 d8a/b three-state digital output, bit 8. depending on status of a/b, output data reflects channel a or channel b data. 44 d9a/b three-state digital output, bit 9 (msb). depending on status of a/b, output data reflects channel a or channel b data. 45 refout internal reference voltage output. may be connected to refin through a resistor or a resistor-divider. 46 refin reference input. v refin = 2 ? (v refp - v refn ). bypass to gnd with a >1nf capacitor. 47 refp positive reference input/output. conversion range is (v refp - v refn ). bypass to gnd with a > 0.1f capacitor. 48 refn negative reference input/output. conversion range is (v refp - v refn ). bypass to gnd with a > 0.1f capacitor.
max1185 dual 10-bit, 20msps, +3v, low-power adc with internal reference and multiplexed parallel outputs ______________________________________________________________________________________ 11 t/h v out x2 flash adc dac 1.5 bits 10 v ina v in stage 1 stage 2 digital correction logic stage 8 stage 9 2-bit flash adc t/h t/h v out x2 flash adc dac 1.5 bits 10 v inb v in stage 1 stage 2 digital correction logic stage 8 stage 9 2-bit flash adc t/h output multiplexer 10 d0a/b ?d9a/b figure 1. pipelined architecture?tage blocks s3b s3a com s5b s5a inb+ inb- s1 out out c2a c2b s4c s4a s4b c1b c1a internal bias internal bias com hold hold clk internal nonoverlapping clock signals track track s2a s2b s3b s3a com s5b s5a ina+ ina- s1 out out c2a c2b s4c s4a s4b c1b c1a internal bias internal bias com s2a s2b max1185 figure 2. max1185 t/h amplifiers
max1185 dual 10-bit, 20msps, +3v, low-power adc with internal reference and multiplexed parallel outputs 12 ______________________________________________________________________________________ analog inputs and reference configurations the full-scale range of the max1185 is determined by the internally generated voltage difference between refp (v dd /2 + v refin /4) and refn (v dd /2 - v refin /4). the full-scale range for both on-chip adcs is adjustable through the refin pin, which is provided for this purpose. refout, refp, com (v dd /2), and refn are internally buffered low-impedance outputs. the max1185 provides three modes of reference operation: internal reference mode buffered external reference mode unbuffered external reference mode in internal reference mode, connect the internal refer- ence output refout to refin through a resistor (e.g., 10k ? ) or resistor-divider, if an application requires a reduced full-scale range. for stability and noise filtering purposes, bypass refin with a >10nf capacitor to gnd. in internal reference mode, refout, com, refp, and refn become low-impedance outputs. in buffered external reference mode, adjust the reference voltage levels externally by applying a stable and accu- rate voltage at refin. in this mode, com, refp, and refn become outputs. refout may be left open or con- nected to refin through a >10k ? resistor. in unbuffered external reference mode, connect refin to gnd. this deactivates the on-chip reference buffers for refp, com, and refn. with their buffers shut down, these nodes become high impedance and may be driven through separate, external reference sources. clock input (clk) the max1185 s clk input accepts cmos-compatible clock signals. since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jit- ter and fast rise and fall times (< 2ns). in particular, sam- pling occurs on the rising edge of the clock signal, requiring this edge to provide lowest possible jitter. any significant aperture jitter would limit the snr performance of the on-chip adcs as follows: snr db = 20 x log 10 (1 / [2 x f in x t aj ]) where f in represents the analog input frequency and t aj is the time of the aperture jitter. clock jitter is especially critical for undersampling appli- cations. the clock input should always be considered as an analog input and routed away from any analog input or other digital signal lines. the max1185 clock input operates with a voltage thresh- old set to v dd /2. clock inputs with a duty cycle other than 50%, must meet the specifications for high and low periods as stated in the electrical characteristics . system timing requirements figure 3 shows the relationship between clock and analog input, a/b indicator, and the resulting cha/chb data output. cha and chb data are sampled on the rising edge of the clock signal. following the rising edge of the 5th clock cycles, the digitized value of the original cha sample is presented at the output, fol- lowed one half-clock cycle later by the digitized value of the original chb sample. a channel selection signal (a/b indicator) allows the user to determine which output data represents which input channel. with a/b = 1, digitized data from cha is present at the output and with a/b = 0 digitized data from chb is present. digital output data, output data format selection (t/b), output enable ( oe ), channel selection (a/b) all digital outputs, d0a/b d9a/b (cha or chb data) and a/b are ttl/cmos logic-compatible. the output coding can be chosen to be either offset binary or two s comple- ment (table 1) controlled by a single pin (t/b). pull t/b low to select offset binary and high to activate two s com- plement output coding. the capacitive load on the digital outputs d0a/b d9a/b should be kept as low as possible (<15pf), to avoid large digital currents that could feed back into the analog portion of the max1185, thereby degrading its dynamic performance. using buffers on the digital outputs of the adcs can further isolate the digital outputs from heavy capacitive loads. to further improve the dynamic performance of the max1185, small-series resistors (e.g., 100 ? ) may be added to the digital output paths close to the max1185. figure 4 displays the timing relationship between output enable and data output valid as well as power- down/wake-up and data output valid. power-down (pd) and sleep (sleep) modes the max1185 offers two power-save modes sleep and full power-down mode. in sleep mode (sleep = 1), only the reference bias circuit is active (both adcs are disabled), and current consumption is reduced to 2.8ma. to enter full power-down mode, pull pd high. with oe simultaneously low, all outputs are latched at the last value prior to the power-down. pulling oe high forces the digital outputs into a high-impedance state.
max1185 dual 10-bit, 20msps, +3v, low-power adc with internal reference and multiplexed parallel outputs ______________________________________________________________________________________ 13 applications information figure 5 depicts a typical application circuit containing two single-ended to differential converters. the internal reference provides a v dd /2 output voltage for level shifting purposes. the input is buffered and then split to a voltage follower and inverter. one lowpass filter per adc suppresses some of the wideband noise associat- ed with high-speed operational amplifiers that follows the amplifiers. the user may select the r iso and c in values to optimize the filter performance, to suit a par- ticular application. for the application in figure 5, a r iso of 50 ? is placed before the capacitive load to prevent ringing and oscillation. the 22pf c in capacitor acts as a small bypassing capacitor. using transformer coupling an rf transformer (figure 6) provides an excellent solution to convert a single-ended source signal to a fully differential signal, required by the max1185 for optimum performance. connecting the center tap of the transformer to com provides a v dd /2 dc level shift to the input. although a 1:1 transformer is shown, a step- up transformer may be selected to reduce the drive requirements. a reduced signal swing from the input driver, such as an op amp, may also improve the over- all distortion. in general, the max1185 provides better sfdr and thd with fully differential input signals than single- ended drive, especially for very high input frequencies. in differential input mode, even-order harmonics are lower as both inputs (ina+, ina- and/or inb+, inb-) are balanced, and each of the adc inputs only requires half the signal swing compared to single-ended mode. t dob t cl t ch t clk t doa t da/b 5 clock-cycle latency (cha), 5.5 clock-cycle latency (chb) a/b chb d0a/b-d9a/b d0b cha d1a chb d1b cha d2a chb d2b cha d3a chb d3b cha d4a chb d4b cha d5a chb d5b cha d6a chb d6b cha chb clk output d0a/b d9a/b oe t disable t enable high-z high-z valid data figure 3. timing diagram for multiplexed outputs figure 4. output timing diagram
max1185 dual 10-bit, 20msps, +3v, low-power adc with internal reference and multiplexed parallel outputs 14 ______________________________________________________________________________________ table 1. max1185 output codes for differential inputs * v ref = v refp - v refn differential input voltage* differential input straight offset binary t/b = 0 two s complement t/b = 1 v ref x 511/512 +full scale - 1lsb 11 1111 1111 01 1111 1111 v ref x 1/512 + 1 lsb 10 0000 0001 00 0000 0001 0 bipolar zero 10 0000 0000 00 0000 0000 - v ref x 1/512 - 1 lsb 01 1111 1111 11 1111 1111 -v ref x 511/512 - full scale + 1 lsb 00 0000 0001 10 0000 0001 -v ref x 512/512 - full scale 00 0000 0000 10 0000 0000 single-ended ac-coupled input signal figure 7 shows an ac-coupled, single-ended applica- tion. amplifiers like the max4108 provide high speed, high bandwidth, low noise, and low distortion to maintain the integrity of the input signal. typical qam demodulation application the most frequently used modulation technique for digital communications applications is probably the quadrature amplitude modulation (qam). typically found in spread- spectrum based systems, a qam signal represents a carrier frequency modulated in both amplitude and phase. at the transmitter, modulating the baseband sig- nal with quadrature outputs, a local oscillator followed by subsequent up-conversion can generate the qam signal. the result is an in-phase (i) and a quadrature (q) carrier component, where the q component is 90 degree phase- shifted with respect to the in-phase component. at the receiver, the qam signal is divided down into it s i and q components, essentially representing the modulation process reversed. figure 8 displays the demodulation process performed in the analog domain, using the dual matched +3.3v, 10-bit adc max1185 and the max2451 quadrature demodulator to recover and digitize the i and q baseband signals. before being digitized by the max1185, the mixed down-signal components may be fil- tered by matched analog filters, such as nyquist or pulse-shaping filters. these remove any unwanted images from the mixing process, thereby enhancing the overall signal-to-noise (snr) performance and minimizing intersymbol interference. grounding, bypassing, and board layout the max1185 requires high-speed board layout design techniques. locate all bypass capacitors as close to the device as possible, preferably on the same side as the adc, using surface-mount devices for minimum inductance. bypass v dd , refp, refn, and com with two parallel 0.1f ceramic capacitors and a 2.2f bipolar capacitor to gnd. follow the same rules to bypass the digital supply (ov dd ) to ognd. multilayer boards with separated ground and power planes pro- duce the highest level of signal integrity. consider the use of a split ground plane arranged to match the physical location of the analog ground (gnd) and the digital output driver ground (ognd) on the adc s package. the two ground planes should be joined at a single point such that the noisy digital ground currents do not interfere with the analog ground plane. the ideal location of this connection can be determined experi- mentally at a point along the gap between the two ground planes, which produces optimum results. make this connection with a low-value, surface-mount resistor (1 ? to 5 ? ), a ferrite bead, or a direct short. alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy digital systems ground plane (e.g., downstream output buffer or dsp ground plane). route high-speed digital signal traces away from the sensitive analog traces of either channel. make sure to isolate the analog input lines to each respective converter to minimize channel- to-channel crosstalk. keep all signal lines short and free of 90 degree turns.
max1185 dual 10-bit, 20msps, +3v, low-power adc with internal reference and multiplexed parallel outputs ______________________________________________________________________________________ 15 figure 5. typical application for single-ended to differential conversion input 300 ? -5v +5v 0.1 f 0.1 f 0.1 f -5v 600 ? 300 ? 300 ? ina+ ina- lowpass filter com 600 ? +5v -5v 0.1 f 600 ? 300 ? 600 ? 300 ? 0.1 f 0.1 f 0.1 f +5v 0.1 f 300 ? max4108 max1185 inb+ inb- max4108 max4108 lowpass filter input 300 ? -5v +5v 0.1 f 0.1 f 0.1 f c in 22pf -5v 600 ? 300 ? 300 ? lowpass filter 600 ? +5v -5v 0.1 f 600 ? 300 ? 600 ? 300 ? 0.1 f 0.1 f 0.1 f +5v 0.1 f 300 ? max4108 max4108 max4108 300 ? lowpass filter r is0 50 ? c in 22pf r is0 50 ? c in 22pf r is0 50 ? c in 22pf r is0 50 ?
max1185 dual 10-bit, 20msps, +3v, low-power adc with internal reference and multiplexed parallel outputs 16 ______________________________________________________________________________________ figure 6. transformer-coupled input drive max1185 t1 n.c. v in 6 1 5 2 4 3 22pf 22pf 0.1 f 0.1 f 2.2 f 25 ? 25 ? minicircuits tt1 6 t1 n.c. v in 6 1 5 2 4 3 22pf 22pf 0.1 f 0.1 f 2.2 f 25 ? 25 ? minicircuits tt1 6 ina- ina+ inb- inb+ com static parameter definitions integral nonlinearity (inl) integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. the static lin- earity parameters for the max1185 are measured using the best straight-line fit method. differential nonlinearity (dnl) differential nonlinearity is the difference between an actual step width and the ideal value of 1lsb. a dnl error specification of less than 1lsb guarantees no missing codes and a monotonic transfer function. dynamic parameter definitions aperture jitter figure 9 depicts the aperture jitter (t aj ), which is the sample-to-sample variation in the aperture delay. aperture delay aperture delay (t ad ) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken (figure 9). signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital samples, the theoretical maximum snr is the ratio of the full-scale analog input (rms value) to the rms
quantization error (residual error). the ideal, theoretical minimum analog-to-digital noise is caused by quantiza- tion error only and results directly from the adc s reso- lution (n-bits): snr db[max] = 6.02 db x n + 1.76 db in reality, there are other noise sources besides quanti- zation noise: thermal noise, reference noise, clock jitter, etc. snr is computed by taking the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamental, the first five har- monics, and the dc offset. signal-to-noise plus distortion (sinad) sinad is computed by taking the ratio of the rms sig- nal to all spectral components minus the fundamental and the dc offset. effective number of bits (enob) enob specifies the dynamic performance of an adc at a specific input frequency and sampling rate. an ideal adcs error consists of quantization noise only. enob is computed from: enob sinad db db db = ? 176 602 . . max1185 dual 10-bit, 20msps, +3v, low-power adc with internal reference and multiplexed parallel outputs ______________________________________________________________________________________ 17 ______________________________________________________________________________________ 17 max1185 0.1 f 1k ? 1k ? 100 ? 100 ? c in 22pf c in 22pf inb+ inb- com ina+ ina- 0.1 f r iso 50 ? r iso 50 ? refp refn v in max4108 0.1 f 1k ? 1k ? 100 ? 100 ? c in 22pf c in 22pf 0.1 f r iso 50 ? r iso 50 ? refp refn v in max4108 figure 7: using an op amp for single-ended, ac-coupled input drive
max1185 total harmonic distortion (thd) thd is typically the ratio of the rms sum of the first four harmonics of the input signal to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 through v 5 are the amplitudes of the 2nd- through 5th-order harmonics. spurious-free dynamic range (sfdr) sfdr is the ratio expressed in decibels of the rms amplitude of the fundamental (maximum signal compo- nent) to the rms value of the next largest spurious component, excluding dc offset. intermodulation distortion (imd) the two-tone imd is the ratio expressed in decibels of either input tone to the worst 3rd-order (or higher) inter- modulation products. the individual input tone levels are at -6.5db full scale and their envelope is at -0.5db full scale. chip information transistor count: 10,811 process: cmos thd vvvv v = +++ ? ? ? ? ? ? ? ? 20 10 2 2 3 2 4 2 5 2 1 log dual 10-bit, 20msps, +3v, low-power adc with internal reference and multiplexed parallel outputs 18 ______________________________________________________________________________________ figure 8. typical qam application, using the max1185 hold analog input sampled data (t/h) t/h t ad t aj track track clk figure 9. t/h aperture timing 0 90 8 downconverter max2451 ina+ a/b cha and chb data alternatingly available on 10-bit, multiplexed output bus max1185 ina- inb+ inb- dsp post processing
max1185 dual 10-bit, 20msps, +3v, low-power adc with internal reference and multiplexed parallel outputs ______________________________________________________________________________________ 19 gnd reference output drivers control t/h t/h pipeline adc dec mux refout refn com refp refin ina+ ina- clk inb+ inb- v dd dec pipeline adc ognd ov dd a/b oe d0a/b d9a/b t/b pd sleep max1185 10 10 functional diagram
max1185 dual 10-bit, 20msps, +3v, low-power adc with internal reference and multiplexed parallel outputs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2001 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information 48l,tqfp.eps

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